In brief: Qualcomm’s next Snapdragon Wear 5100 might not be the mind-blowing upgrade to Wear 4100 that some have been waiting for, but all the hints so far point to improved energy efficiency and a more compact chip package size, both of which are welcome improvements.
Qualcomm has been working on a successor to the Snapdragon Wear 4100 platform, but a new leak suggests the company isn’t all that interested in giving it a significant performance boost. Instead, this will likely be an iterative upgrade that will improve energy efficiency and chip package size more than anything else.
Last month, Wear OS enthusiasts over at XDA Developers spotted the company’s upcoming chipset in code under the “Monaco” codename. At the time, this offered some hope that it could feature Arm’s Cortex-A73 cores just like the Snapdragon 662 and 460 mobile platforms for phones.
However, a new report from WinFuture suggests otherwise — initial samples of the “SW5100” chipset will utilize the same Arm Cortex-A53 cores as the Snapdragon Wear 4100+. In contrast, Samsung’s new Exynos W920 chipset powering the Galaxy Watch4 features Cortex-A55 cores, which are up to 20 percent faster. Not much is known on the GPU front, however, so there’s still hope for the Wear 5100 chipset to look like more than a half measure.
Qualcomm is said to be testing several configurations of the Wear 5100, some of which have two gigabytes of LPDDR4X RAM and either 8 or 16 gigabytes of eMMC storage. The upgrade to LPDDR4X is significant, both in terms of performance and power efficiency. That said, the biggest efficiency gains will come via an improved AON co-processor for the always-on display functions and some of the health and fitness tracking functionality.
It’s worth pointing out that most of the Exynos W920’s energy efficiency improvements come from being manufactured on a 5nm process node. We don’t know the exact process node that Qualcomm will use for the Snapdragon Wear 5100, but the company has been in talks with both Samsung and China’s SMIC to secure manufacturing capacity for the new chip.